1. Field of the Invention
The present invention relates to a semiconductor device of a master slice type.
2. Description of the Prior Art
A gate array is known as a semiconductor device of the master slice type. A CMOS gate array is known as one kind of such gate arrays. FIG. 1 shows an example of a basic cell of a conventional CMOS gate array. As shown in FIG. 1, a basic cell of the conventional CMOS gate array comprises two p-channel MOS transistors T.sub.1 and T.sub.2 and two n-channel MOS transistors T.sub.3 and T.sub.4. Values of W/L (W: channel width, L: channel length) of the p-channel MOS transistors T.sub.1 and T.sub.2 are equal. Values of W/L of the n-channel MOS transistors T.sub.3 and T.sub.4 are also the same. Reference numerals 101 to 104 denote gate electrodes. Reference numerals 105 to 107 indicate p.sup.+ -type semiconductor regions which are used as source regions or drain regions of the p-channel MOS transistors T.sub.1 and T.sub.2. The semiconductor regions 105 to 107 are formed in, for example, an n-well formed in a semiconductor substrate (not shown). On the other hand, reference numerals 108 to 110 indicate, for instance, n.sup.+ -type semiconductor regions which are used as source regions or drain regions of the n-channel MOS transistors T.sub.3 and T.sub.4. The semiconductor regions 108 to 110 are formed in, for example, a p-well formed in the semiconductor substrate (not shown). In this case, the p-channel MOS transistor T.sub.1 is formed by the gate electrode 101 and the semiconductor regions 105 and 106. The p-channel MOS transistor T.sub.2 is formed by the gate electrode 102 and the semiconductor regions 106 and 107. Similarly, the n-channel MOS transistor T.sub.3 is formed by the gate electrode 103 and the semiconductor regions 108 and 109. The n-channel MOS transistor T.sub.4 is formed by the gate electrode 104 and the semiconductor regions 109 and 110. Reference numeral 111 denotes, for instance, an n.sup.+ -type semiconductor region which is used to make a wiring to supply a power source voltage V.sub.DD contact the n-well. Reference numeral 112 indicates, for instance, a p.sup.+ -type semiconductor region which is used to make a wiring to supply a power source voltage V.sub.SS contact the p-well.
There are the following problems in the case of constructing, for instance, a full CMOS type static RAM by the conventional CMOS gate array comprising the basic cell shown in FIG. 1 mentioned above. That is, memory cells of the full CMOS type static RAM are ordinarily constructed by four n-channel MOS transistors and two p-channel MOS transistors. Therefore, in the case of constructing the memory cells of the full CMOS type static RAM by using the basic cells shown in FIG. 1, two such basic cells are needed. In this case, two p-channel MOS transistors remain. That is, in the case of constructing the memory cells of the full CMOS type static RAM by using the basic cells shown in FIG. 1, the half of one basic cell is not used and the use efficiency of the basic cell is low. Thus, it is difficult to improve the integration density of the memory cells.
On the other hand, in the case of constructing a 2-input NAND circuit, a 2-input NOR circuit, an inverter circuit, a transmission circuit, or the like by using the basic cell shown in FIG. 1, the optimum circuit construction cannot be easily obtained due to reasons such that a degree of freedom of wirings among the transistors is small and the like.